Non-volatile memory devices, such as EPROM, EEPROM, and Flash EEPROM, store data even after power is turned off. One common application of EEPROMs is in programmable logic devices (PLDs). PLDs are standard semiconductor components purchased by systems manufacturers in a “blank” state that can be custom configured or programmed (the terms are used interchangeably in the art) into a virtually unlimited number of specific logic functions. PLDs provide system designers with the ability to quickly create custom logic functions to provide product differentiation without sacrificing a rapid time to market. PLDs may be reprogrammable, meaning that the logic configuration can be reconfigured after the initial programming.
One type of PLD is known as a field-programmable gate array (FPGA). An FPGA is a general-purpose device that can be programmed by an end user to perform one or more selected functions. An FPGA typically includes an array of individually configurable logic blocks (CLBs), each of which is programmably interconnected to other CLBs and to input/output (I/O) pins via a programmable routing structure to provide the selected function. Examples of such devices are exemplified in U.S. Pat. Nos. 4,642,487; 4,706,216; and 4,758,985.
An FPGA device can be characterized as an integrated circuit that may include four major features:
(1) A user-accessible, configurable memory device (e.g., SRAM, EPROM, EEPROM, anti-fused, fused, etc.) is provided in the FPGA device so as to be at least once-programmable by device users for defining user-provided configuration instructions. Static Random Access Memory, or SRAM, is a form of reprogrammable memory that may be programmed differently many times. Electrically Erasable Programmable ROM, or EEPROM, is another example of nonvolatile reprogrammable memory. The configurable memory of an FPGA device may be formed of a mixture of different kinds of memory elements if desired (e.g., SRAM and EEPROM).
(2) Input/Output Blocks (IOBs) are provided for interconnecting other internal circuit components of the FPGA device with external circuitry. The IOBs may have fixed configurations, or they may be configurable in accordance with user-provided configuration instructions.
(3) CLBs are provided for carrying out user-programmed logic functions (e.g., logic gates) as defined by user-provided configuration instructions. For instance, one or more CLBs may be configured to operate as a state machine. Typically, each of the many CLBs of an FPGA has at least one lookup table (LUT) that is user-configurable to define any desired truth table. A CLB may have other resources such as LUT input signal pre-processing resources and LUT output signal post-processing resources. Although the term “CLB” was adopted by early pioneers of FPGA technology, it is not uncommon to see other names being given to the repeated portion of the FPGA that carries out user-programmed logic functions. An example of another name often associated with a repeated portion of an FPGA is a Generic Logic Block (GLB).
(4) An interconnect network is provided for carrying signal traffic within the FPGA device between various CLBs and/or between various IOBs and/or between various IOBs and CLBs. At least part of the interconnect network is typically configurable so as to allow for programmably-defined routing of signals between various CLBs and/or IOBs in accordance with user-defined routing instructions.
Most FPGAs have these four features, but modern FPGAs tend to be even more complex. For example, many CLBs can be configured together to implement such devices as multipliers or complex microprocessors. For example, U.S. Pat. No. 5,754,459, issued May 19, 1998 to Telikepalli, teaches implementing a multiplier circuit using a number of CLBs in an FPGA architecture. However, implementing a multiplier using CLBs of an FPGA architecture may not only consume valuable CLB resources, but also consume valuable general interconnect resources, which in turn may slow performance of the FPGA device. Consequently, preconfigured, dedicated multipliers have been inserted into some FPGA designs in order to free valuable CLB resources for other functions, such as illustrated in U.S. Pat. No. 6,362,650 to New, et al.